The present invention relates to a lateral double-diffused field effect transistor, and typically relates to a lateral double-diffused MOS transistor.
The present invention also relates to an integrated circuit having such a lateral double-diffused field effect transistor.
In recent years, with progress of multifunctional electronic equipment, semiconductor devices used therefor are diversified and the semiconductor devices are required to have high breakdown voltage, high power, downsizing, and low power consumption. In order to accomplish the lower power consumption, transistors with low on-resistance are necessary.
FIG. 6 shows a cross sectional structure of a general lateral double-diffused MOS transistor (see, e.g., JP H08-321614 A). The lateral double-diffused MOS transistor is an N-channel MOS transistor, which is formed on a lightly-doped N-well diffusion layer 102 provided on the surface of a P-substrate 101. The lateral double-diffused MOS transistor is composed of a P-body diffusion layer 103, a gate electrode 105 formed over the surfaces of an N+ source diffusion layer 106 and the N-well diffusion layer 102 through a gate oxide 104, as well as the N+ source diffusion layer 106 and an N+ drain diffusion layer 107 formed in a self-aligning way across the gate electrode 105. A region which is a surface portion immediately below the gate electrode 105 in the p-body diffusion layer 103 and which is between the N+ source diffusion layer 106 and the N-well diffusion layer 102 is a channel region, while a surface portion of the N-well diffusion layer 102 is a drift drain region. It is to be noted that the p-body diffusion layer 103 is short-circuited to the N+ diffusion layer 106 through a P+ diffusion layer 108 by an unshown interconnection. Thus, the p-body diffusion layer 103 and the N+ source diffusion layer 106 are made equal in potential, by which the operation of a parasitic NPN transistor is prevented.
FIG. 7A shows a plan pattern layout of a gate electrode G, a source diffusion layer S and a drain diffusion layer D in a general lateral double-diffused MOS transistor. In the plan pattern layout, the source diffusion layer S and the drain diffusion layer D, which extend in one direction (vertical direction in FIG. 7A) in parallel with each other, are placed alternately in a direction perpendicular to the one direction. The gate electrode G covers the channel region between the source diffusion layer S and the drain diffusion layer D.
The on-resistance of the MOS transistor is in close relationship with its size, that is, the larger size can reduce the on-resistance, although this causes increase in chip size and manufacturing costs. Therefore, the performance of the transistors is generally discussed based on on-resistance Ron*A per unit area. In order to reduce the Ron*A, a plan pattern layout as shown in FIG. 7B has been proposed. In this plan pattern layout, the source diffusion layer S and the drain diffusion D are square regions, and the drain diffusion layers D are placed so as to face four sides of a given source diffusion layer S. In such a case, a number of drain current flowing routes are secured, and therefore the Ron*A can be reduced.
The lateral double-diffused MOS transistor is required to have low on-resistance with an identical area and high breakdown voltage of the drain. In the structure of FIG. 6, the breakdown voltage (meaning drain breakdown voltage as hereinbelow) is determined by a distance between the p-body diffusion layer 103 and the N+ drain diffusion layer 107 (a length of the drift drain region) and by the concentration of the N-well diffusion layer 102. The longer drift drain region and the lower concentration of the N-well diffusion layer 102 increase the breakdown voltage. If the on-resistance is reduced with an identical area by, for example, increasing the concentration of the N-well diffusion layer 102, then the breakdown voltage is decreased. It can be said that the breakdown voltage and the on-resistance is in a trade-off relationship.
In order to increase the length of the drift drain region with an identical area, conventionally there are proposals in which a portion of the N-well diffusion layer 102 along the N+ drain diffusion layer 107 is oxidized to form a LOCOS (local oxide) 110 as shown in FIG. 8 and in which a deep trench 111 is formed to further deepen the LOCOS 110 as shown in FIG. 9.
However, in the case of forming the LOCOS 110 as shown in FIG. 8 and FIG. 9, an electric field may concentrate on the edge of the LOCOS 110, resulting in decrease in the breakdown voltage. Particularly in the case of adopting the plan pattern layout of FIG. 7B, an electric field concentrates on the vicinity of the corner portions of the drain diffusion layer D, and so the breakdown voltage is further decreased. This causes a problem of inability in increasing the breakdown voltage.